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integrated silicon solution, inc. ? 1-800-379-4774 1 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? this document contains preliminary information data. issi reserves the right to make changes to its products at any time witho ut notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1998, integrat ed silicon solution, inc. features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control pentium? or linear burst sequence control using mode input three chip enables for simple depth expansion and address pipelining common data inputs and data outputs jedec 100-pin tqfp and 119-pin pbga package single +3.3v, +10%, ?5% power supply power-down snooze mode description the issi is61sp12832 and IS61SP12836 is a high-speed synchronous static ram designed to provide a burstable, high-performance memory for high speed networking and communication applications. it is organized as 131,072 words by 32 bits and 36 bits, fabricated with issi 's ad- vanced cmos technology. the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all syn- chronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. bw1 controls dqa, bw2 controls dqb, bw3 controls dqc, bw4 controls dqd, conditioned by bwe being low. a low on gw input would cause all bytes to be written. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. preliminary information march 2000 fast access time symbol parameter -200 -166 -150 -133 -5 units t kq clock access time 3.1 3.5 3.8 4 5 ns t kc cycle time 5 6 6.7 7.5 10 ns frequency 200 166 150 133 100 mhz 128k x 32, 128k x 36 synchronous pipelined static ram
is61sp12832 IS61SP12836 issi ? 2 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 04/04/00 block diagram 17 binary counter a16-a0 bw1 gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 15 17 address register ce d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bw4 ce ce2 ce2 bw2 bw3 128k x 32/128k x 36 memory array 32 or 36 input registers clk output registers clk 32 or 36 oe 4 32 or 36 oe dq[31:0] or dq[35:0]
integrated silicon solution, inc. ? 1-800-379-4774 3 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? pin configuration pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a16 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bw1 - bw4 individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v zz snooze enable a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq a6 ce2 a7 nc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 nc a5 nc nc a4 a3 a2 gnd gnd gnd bw3 gnd nc gnd bw4 gnd gnd gnd mode a10 nc adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc a11 nc a8 a9 a12 gnd gnd gnd bw2 gnd nc gnd bw1 gnd gnd gnd nc a14 nc a16 ce2 a15 nc dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 nc a13 nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 nc dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd nc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 nc a6 a7 ce ce2 bw4 bw3 bw2 bw1 ce2 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 nc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc nc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 128k x 32 119-pin pbga (top view) 100-pin tqfp
is61sp12832 IS61SP12836 issi ? 4 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 04/04/00 pin configuration pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2 - a16 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bw1 - bw4 individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v zz snooze enable dqpa-dqpd parity data i/o a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq a6 ce2 a7 dqpc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 dqpd a5 nc nc a4 a3 a2 gnd gnd gnd bw3 gnd nc gnd bw4 gnd gnd gnd mode a10 nc adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc a11 nc a8 a9 a12 gnd gnd gnd bw2 gnd nc gnd bw1 gnd gnd gnd nc a14 nc a16 ce2 a15 dqpb dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 dqpa a13 nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 dqpb dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd nc vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 dqpa a6 a7 ce ce2 bw4 bw3 bw2 bw1 ce2 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 dqpc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc nc gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 128k x 36 119-pin pbga (top view) 100-pin tqfp
integrated silicon solution, inc. ? 1-800-379-4774 5 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? truth table address operation used ce ce2 ce2 adsp adsc adv write oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l xxxx high-z deselected, power-down none l l x l xxxx high-z deselected, power-down none x x h h l x x x high-z deselected, power-down none x l x h l x x x high-z read cycle, begin burst external l h l l xxxxq read cycle, begin burst external l h l h l x read x q write cycle, begin burst external l h l h l x w rite x d read cycle, continue burst next x x x h h l read l q read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h x x x h l read l q read cycle, continue burst next h x x x h l read h high-z write cycle, continue burst next x x x h h l write x d write cycle, continue burst next h x x x h l write x d read cycle, suspend burst current x x x h h h read l q read cycle, suspend burst current x x x h h h read h high-z read cycle, suspend burst current h x x x h h read l q read cycle, suspend burst current h x x x h h read h high-z write cycle, suspend burst current x x x h h h w rite x d write cycle, suspend burst current h x x x h h w rite x d partial truth table function gw bwe bw1 bw2 bw3 bw4 read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes h lllll write all bytes l xxxxx
is61sp12832 IS61SP12836 issi ? 6 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 04/04/00 interleaved burst address table (mode = v cc or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias ? 40 to +85 c t stg storage temperature ? 55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ? 0.5 to v ccq + 0.3 v v in voltage relative to gnd for ? 0.5 to v cc + 0.5 v for address and control inputs v cc voltage on vcc supply relatiive to gnd ? 0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
integrated silicon solution, inc. ? 1-800-379-4774 7 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v, +10%, ? 5% industrial ? 40 c to +85 c 3.3v, +10%, ? 5% dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = ? 4.0 ma 2.4 ? v v ol output low voltage i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v ccq + 0.3 v v il input low voltage ? 0.3 0.8 v i li input leakage current gnd v in v ccq (2) com. ? 22a ind. ? 55 i lo output leakage current gnd v out v ccq , oe = v ih com. ? 22a ind. ? 55 power supply characteristics (over operating range) -200 -166 - 150 - 133 -5 symbol parameter test conditions max. max. max. max max. uni t i cc ac operating device selected, com. 310 290 270 230 210 ma supply current all inputs = v il or v ih ind. ? 300 280 240 220 ma oe = v ih , vcc = max. cycle time t kc min. i sb standby current device deselected, com. 70 70 70 70 65 ma v cc = max., ind. ? 80 80 80 75 ma all inputs = v ih or v il clk cycle time t kc min. i zz power-down mode zz = v cc com. 15 15 15 15 15 ma current clock running ind. 20 20 20 20 20 ma all inputs gnd + 0.2v or vcc ? 0.2v notes: 1. the mode pin has an internal pullup. this pin may be a no connect, tied to gnd, or tied to v cc . 2. the mode pin should be tied to vcc or gnd. it exhibits 10 a maximum leakage current when tied to gnd + 0.2v or vcc ? 0.2v.
is61sp12832 IS61SP12836 issi ? 8 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 04/04/00 capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 3.3v. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads output buffer z o = 50 ? 1.5v 50 ? 30 pf 317 ? 5 pf including jig and scope 351 ? output 3.3v figure 1 figure 2
integrated silicon solution, inc. ? 1-800-379-4774 9 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? read/write cycle switching characteristics (over operating range) - 200 - 166 -150 -133 -5 symbol parameter min. max. min. max. min. max. min. max. min. max. unit f max (3) clock frequency ? 200 ? 166 ? 150 ? 133 ? 100 mhz t kc (3) cycle time 5 ? 6 ? 6.7 ? 7.5 ? 10 ? ns t kh clock high time 2.3 ? 2.4 ? 2.6 ? 2.8 ? 3 ? ns t kl (3) clock low time 2.3 ? 2.4 ? 2.6 ? 2.8 ? 3 ? ns t kq (3) clock access time ? 3.1 ? 3.5 ? 3.8 ? 4 ? 5ns t kqx (1) clock high to output invalid 3 ? 3 ? 3 ? 3 ? 3 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? 0 ? 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 ns t oeq (3) output enable to output valid ? 3.1 ? 3.5 ? 3.5 ? 3.8 ? 5ns t oeqx (1) output disable to output invalid 0 ? 0 ? 0 ? 0 ? 0 ? ns t oelz (1,2) output enable to output low-z 0 ? 0 ? 0 ? 0 ? 0 ? ns t oehz (1,2) output disable to output high-z 2 3 2 3.5 2 3.5 2 3.8 2 5 ns t as (3) address setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ss (3) address status setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ws (3) write setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ces (3) chip enable setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t avs (3) address advance setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ah (3) address hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t sh (3) address status hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t wh (3) write hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t ceh (3) chip enable hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t avh (3) address advance hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2. 3. tested with load in figure 1.
is61sp12832 IS61SP12836 issi ? 10 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 04/04/00 read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bw4-bw1 bwe gw a16-a0 adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b
integrated silicon solution, inc. ? 1-800-379-4774 11 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? write cycle switching characteristics (over operating range) - 200 - 166 -150 -133 -5 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t kc (1) cycle time 5 ? 6 ? 6.7 ? 7.5 ? 10 ? ns t kh (1) clock high time 2.3 ? 2.4 ? 2.6 ? 2.8 ? 4 ? ns t kl (1) clock low time 2.3 ? 2.4 ? 2.6 ? 2.8 ? 4 ? ns t as (1) address setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ss (1) address status setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ws (1) write setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ds (1) data in setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ces (1) chip enable setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t avs (1) address advance setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ah (1) address hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t sh (1) address status hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t dh (1) data in hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t wh (1) write hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t ceh (1) chip enable hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t avh (1) address advance hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns note: 1. tested with load in figure 1.
is61sp12832 IS61SP12836 issi ? 12 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 04/04/00 write cycle timing single write data out data in oe ce2 ce2 ce bw4-bw1 bwe gw a16-a0 adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
integrated silicon solution, inc. ? 1-800-379-4774 13 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? snooze and recovery cycle switching characteristics (over operating range) -200 - 166 -150 -133 -5 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t kc (3) cycle time 5 ? 6 ? 6.7 ? 7.5 ? 10 ? ns t kh (3) clock high time 2.3 ? 2.4 ? 2.6 ? 2.8 ? 4 ? ns t kl (3) clock low time 2.3 ? 2.4 ? 2.6 ? 2.8 ? 4 ? ns t kq (3) clock access time ? 3.1 ? 3.5 ? 3.8 ? 4 ? 5ns t kqx (1) clock high to output invalid 3 ? 1.5 ? 1.5 ? 1.5 ? 2.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? 0 ? 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 ns t oeq (3) output enable to output valid ? 3.1 ? 3.5 ? 3.5 ? 3.9 ? 5ns t oeqx (1) output disable to output invalid 0 ? 0 ? 0 ? 0 ? 0 ? ns t oelz (1,2) output enable to output low-z 0 ? 0 ? 0 ? 0 ? 0 ? ns t oehz (1,2) output disable to output high-z 2 3 2 3.5 2 3.5 2 3.8 2 5 ns t as (3) address setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ss (3) address status setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ces (3) chip enable setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? 2 ? ns t ah (3) address hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t sh (3) address status hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t ceh (3) chip enable hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t zzs zz standby 2 ? 2 ? 2 ? 2 ? 2 ? cyc t zzrec zz recovery 2 ? 2 ? 2 ? 2 ? 2 ? cyc notes: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2. 3. tested with load in figure 1.
is61sp12832 IS61SP12836 issi ? 14 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00b 04/04/00 snooze and recovery cycle timing single read high-z high-z data out data in zz oe ce2 ce2 ce bw4-bw1 bwe gw a16-a0 adv adsc adsp clk rd1 1a read snooze with data retention t kc t kl t kh t ss t sh t as t ah rd2 t ces t ceh t ces t ceh t ces t ceh t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz t zzs t zzrec
integrated silicon solution, inc. ? 1-800-379-4774 15 preliminary information rev. 00b 04/04/00 is61sp12832 IS61SP12836 issi ? ordering information commercial range: 0 c to +70 c speed order part number package 200 mhz IS61SP12836-200tq tqfp IS61SP12836-200b pbga 166 mhz IS61SP12836-166tq tqfp IS61SP12836-166b pbga 150 mhz IS61SP12836-150tq tqfp IS61SP12836-150b pbga 133 mhz IS61SP12836-133tq tqfp IS61SP12836-133b pbga 5 ns IS61SP12836-5tq tqfp IS61SP12836-5b pbga industrial range: ? 40 c to +85 c speed order part number package 166 mhz IS61SP12836-166tqi tqfp 150 mhz IS61SP12836-150tqi tqfp 133 mhz IS61SP12836-133tqi tqfp 5 ns IS61SP12836-5tqi tqfp issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information commercial range: 0 c to +70 c speed order part number package 200 mhz is61sp12832-200tq tqfp is61sp12832-200b pbga 166 mhz is61sp12832-166tq tqfp is61sp12832-166b pbga 150 mhz is61sp12832-150tq tqfp is61sp12832-150b pbga 133 mhz is61sp12832-133tq tqfp is61sp12832-133b pbga 5 ns is61sp12832-5tq tqfp is61sp12832-5b pbga industrial range: ? 40 c to +85 c speed order part number package 166 mhz is61sp12832-166tqi tqfp 150 mhz is61sp12832-150tqi tqfp 133 mhz is61sp12832-133tqi tqfp 5 ns is61sp12832-5tqi tqfp

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